1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device.
2. Related Art
Besides motor control inverters, power devices are widely utilized in a large number of fields, such as a power supply application of a PDP (plasma display panel), liquid crystal panel, or the like, with a large capacitive load, or an inverter application for household appliances such as air conditioners or lighting. In recent years, owing to advances in LSI technology, high voltage ICs (HVIC: High Voltage Integrated Circuit) wherein a high voltage of up to 1,200V is ensured have been put to practical use.
ICs wherein upper and lower arm driver functions are mounted on one silicon chip, and furthermore, ICs wherein a control circuit or power semiconductor device is also mounted on one silicon chip, and the like, are grouped as HVICs, and also contribute to increased efficiency and a reduction in part quantities as whole inverters. A description will be given of a circuit configuration of a high voltage IC, with a motor control inverter including a motor as a load as an example. FIG. 9 is a circuit diagram showing a configuration of a main portion (one phase) of a high voltage driver IC. FIG. 10 is a characteristic diagram showing fluctuation of an intermediate potential Vs when a power module 100 operates. FIG. 10 shows the intermediate potential Vs fluctuation of a connection point 105 when a first MOSFET 101 and second MOSFET 102 are turned on and off in a complementary way.
As shown in FIG. 9, a drive circuit 111 is a circuit that drives the power module 100. The power module 100 is a single phase inverter circuit wherein the high side first MOSFET (insulated gate field effect transistor) 101 (upper arm output element) and the low side second MOSFET 102 (lower arm output element) are connected in series, and drives a motor 112, which is the load. Reference sign 103 and reference sign 104 are FWDs (freewheeling diodes).
The drain of the first MOSFET 101 is connected to a main power supply Vds. The source of the first MOSFET 101 is connected to the drain of the second MOSFET 102. The source of the second MOSFET 102 is connected to the ground. The connection point 105 of the source of the first MOSFET 101 and the drain of the second MOSFET 102 is an output point of a main circuit formed of the power module 100.
The intermediate potential Vs fluctuates by repeatedly rising (hereafter referred to as a first state 121) and falling (hereafter referred to as a second state 122) between a high potential side potential (for example, 400V) and a low potential side potential (for example, a ground potential GND of 0V) of the main power supply Vds in accordance with the first MOSFET 101 and second MOSFET 102 being turned on and off in a complementary way (FIG. 10).
The drive circuit 111 has a control unit, high side drive circuit, low side drive circuit, and level shifter, omitted from the drawing. The high side drive circuit operates in accordance with a high side power supply potential VB applied to a VB terminal having the intermediate potential Vs applied to a Vs terminal as a reference, thus driving the first MOSFET 101. The low side drive circuit operates in accordance with a low side power supply potential Vcc applied to a Vcc terminal having the ground potential GND as a reference, thus driving the second MOSFET 102.
Specifically, a low side level turn-on/turn-off signal output from the control unit is input via the low side drive circuit from a low side output terminal LO into the gate of the second MOSFET 102. Also, the low side level turn-on/turn-off signal is converted by the level shifter into a high side level turn-on/turn-off signal. The high side level turn-on/turn-off signal is input via the high side drive circuit from a high side output terminal HO into the gate of the first MOSFET 101.
An HIN terminal and LIN terminal are respectively a high side control signal input terminal and low side control signal input terminal that form references when the high side level turn-on/turn-off signal and low side level turn-on/turn-off signal are generated in the drive circuit 111. Each input/output terminal of the drive circuit 111 is normally connected to a computer such as a microcomputer, and the drive circuit 111 is controlled by a program prepared in advance being executed by the computer, whereby control of the whole high voltage driver IC is carried out.
In this kind of motor control inverter, the main power supply Vds is normally a high voltage of 100V to 400V AC (alternating current). In particular, in the first state 121 wherein the first MOSFET 101 is in an on-state and the second MOSFET 102 is in an off-state, the source potential of the first MOSFET 101 is a high potential. As it is necessary for the gate potential to be higher still than the source potential in order to drive the first MOSFET 101, a photocoupler (PC) or high voltage IC (HVIC) that can be used with a high voltage power supply is used as the drive circuit 111.
A description will be given of the structure of a heretofore known high side drive circuit. FIG. 11 is a plan view showing a planar structure of the heretofore known high side drive circuit. FIG. 12 is a sectional view showing a sectional structure along a section line AA-AA′ of FIG. 11. As shown in FIGS. 11 and 12, a high side drive circuit formation region 130, in which the high side drive circuit is formed, and a high voltage termination region (HVJT: High Voltage Junction Termination) 140, which ensures the breakdown voltage of the high side drive circuit, are formed in a p-type semiconductor substrate (semiconductor chip) 131.
An n-type isolation region 132 is selectively formed in a surface layer of the p-type semiconductor substrate 131. A lateral p-channel MOSFET (MV-PMOS) 133 and lateral n-channel MOSFET (MV-NMOS) 134 configuring the high side drive circuit are formed in a surface layer of the n-type isolation region 132. The MV-NMOS 134 is formed in a p-type isolation region 135 provided in a surface layer of the n-type isolation region 132. Also, a p-type region 141 is formed in the HVJT 140 in a surface layer of the p-type semiconductor substrate 131 on the outer side of the n-type isolation region 132.
The ground potential GND is applied to the p-type region (hereafter referred to as the p-type GND region) 141. The high side power supply potential VB is applied to the n-type isolation region 132 via an n++ type region 151, or the like. By the first MOSFET 101 and second MOSFET 102 configuring the inverter being turned on and off in a complementary way, a surge voltage 121a occurs in the first state 121 wherein the first MOSFET 101 is in an on-state and the second MOSFET 102 is in an off-state, and the intermediate potential Vs transiently rises (FIG. 10).
Meanwhile, in the second state 122 wherein the first MOSFET 101 is in an off-state and the second MOSFET 102 is in an on-state, a negative surge 122a occurs for in the region of a few hundred nanoseconds in the connection point 105 of the first MOSFET 101 and second MOSFET 102 (FIG. 10). When the negative surge 122a occurs, the intermediate potential Vs becomes lower than the ground potential GND. When the high side power supply potential VB also becomes lower than the ground potential GND in accompaniment to this, a parasitic diode formed of the p-type GND region 141 (ground potential GND) and n-type isolation region 132 is turned on, and holes 142 flow from the p-type GND region 141 to the high side drive circuit formation region 130. Because of this, there is a problem in that the high side drive circuit malfunctions.
The following device has been proposed as a high voltage IC that resolves the problem. A p+ type impurity region is formed so as to come in contact with a p-type well in an upper surface of an n-type impurity region between an NMOS and a PMOS. An electrode is formed on the p+ type impurity region, and the electrode is connected to a high voltage side floating offset voltage VS. The impurity concentration of the p+ type impurity region is higher than the impurity concentration of the p-type well, and the p+ type impurity region is formed to be shallower than the p-type well. An n+ type impurity region is formed in the upper surface of the n-type impurity region between the p+ type impurity region and PMOS. An electrode is formed on the n+ type impurity region, and the electrode is connected to a high voltage side floating supply absolute voltage VB. See, for example, Japanese Patent Application Publication No. JP-A-2009-231851 (also referred to herein as “PTL 1”).
Also, a device wherein a high voltage diode D3 is provided between a common ground node (COM) and virtual ground node (VS) in the interior of a high voltage control circuit (HVIC) utilizing a common substrate region has been proposed as another device. See, for example, Japanese Patent Application Publication No. JP-A-2010-263116 (also referred to herein as “PTL 2”).
Also, a semiconductor device such that MOS transistors isolated by a first isolation trench are formed, n-fold (n≧2) second isolation trenches are formed, one MOS transistor is disposed in each of n field regions, the n MOS transistors are sequentially connected in series between a ground (GND) potential and a predetermined power supply potential, and output is extracted from between a power supply potential side terminal of an nth stage MOS transistor and an output resistor, wherein the potential of a field region enclosed by the innermost second isolation trench is fixed at the power supply potential, has been proposed as another device. See, for example, Japanese Patent Application Publication No. JP-A-2007-266561 (also referred to herein as “PTL 3”).
The following device has been proposed as a device including a high potential portion and low potential portion isolated by a dielectric region on the same semiconductor substrate. A high voltage junction termination structure portion is provided in a peripheral portion of a high potential gate drive circuit in order to electrically isolate from a low potential gate drive circuit provided on the same semiconductor substrate. Further, trenches are provided in the high voltage junction termination structure portion and between an n+ type source layer and n+ type drain layer of a level shifter circuit portion provided in one portion of the high potential gate drive circuit. Also, oxide films, or the like, are deposited inside the trenches, forming a dielectric region. See, for example, Japanese Patent Application Publication No. JP-A-2009-206284 (also referred to herein as “PTL 4”).
A device including a semiconductor substrate having a plate form cavity in the interior thereof and a passive element formed on the surface of the semiconductor substrate above the cavity has been proposed as a device wherein a dielectric region is provided on a semiconductor substrate. See, for example, Japanese Patent Application Publication No. JP-A-2001-144276 (also referred to herein as “PTL 5”).